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system_stm32l4xx.c File Reference

CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. More...

#include "stm32l4xx.h"
Include dependency graph for system_stm32l4xx.c:

Macros

#define HSE_VALUE   8000000U
 
#define MSI_VALUE   4000000U
 
#define HSI_VALUE   16000000U
 
#define USER_VECT_TAB_ADDRESS
 
#define VECT_TAB_BASE_ADDRESS   FLASH_BASE
 
#define VECT_TAB_OFFSET   0x00000000U
 

Functions

void SystemInit (void)
 Setup the microcontroller system.
 
void SystemCoreClockUpdate (void)
 Update SystemCoreClock variable according to Clock Register Values. The SystemCoreClock variable contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
 

Variables

uint32_t SystemCoreClock = 4000000U
 
const uint8_t AHBPrescTable [16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}
 
const uint8_t APBPrescTable [8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}
 
const uint32_t MSIRangeTable [12]
 

Detailed Description

CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.

Author
MCD Application Team

This file provides two functions and one global variable to be called from user application:

  • SystemInit(): This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32l4xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

After each device reset the MSI (4 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to configure the system clock before to branch to main program.

This file configures the system clock as follows:


System Clock source | MSI

SYSCLK(Hz) | 4000000

HCLK(Hz) | 4000000

AHB Prescaler | 1

APB1 Prescaler | 1

APB2 Prescaler | 1

PLL_M | 1

PLL_N | 8

PLL_P | 7

PLL_Q | 2

PLL_R | 2

PLLSAI1_P | NA

PLLSAI1_Q | NA

PLLSAI1_R | NA

PLLSAI2_P | NA

PLLSAI2_Q | NA

PLLSAI2_R | NA

Require 48MHz for USB OTG FS, | Disabled

SDIO and RNG clock |

=============================================================================

Attention

Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.